User process
   |
   | read(0, buf, n)
   |→ consoleread()      ← (bottom half)
   |     |
   |     | sleep(&input); ← if buffer empty
   ↓
UART input event (interrupt)
   → trap → devintr() → uartintr() ← (top half)
         |  read char from UART
         |  store in input.buf
         |  wakeup(&input)

User process resumes
   |
   | consoleread() returns data
   | read() → back to user space

void
consoleinit(void)
{
  initlock(&cons.lock, "cons");

  uartinit();

  // connect read and write system calls
  // to consoleread and consolewrite.
  devsw[CONSOLE].read = consoleread;
  devsw[CONSOLE].write = consolewrite;
}

void
uartinit(void)
{
  // disable interrupts.
  WriteReg(IER, 0x00);

  // special mode to set baud rate.
  WriteReg(LCR, LCR_BAUD_LATCH);

  // LSB for baud rate of 38.4K.
  WriteReg(0, 0x03);

  // MSB for baud rate of 38.4K.
  WriteReg(1, 0x00);

  // leave set-baud mode,
  // and set word length to 8 bits, no parity.
  WriteReg(LCR, LCR_EIGHT_BITS);

  // reset and enable FIFOs.
  WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);

  // enable transmit and receive interrupts.
  WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE);

  initlock(&uart_tx_lock, "uart");
}

int
main(void)
{
  if(open("console", O_RDWR) < 0){
    mknod("console", CONSOLE, 0);
    open("console", O_RDWR);
  }
  dup(0);  // stdout
  dup(0);  // stderr
}

struct devsw {
  int (*read)(int, uint64, int);
  int (*write)(int, uint64, int);
};

#define CONSOLE 1

void
consoleinit(void)
{
  // connect read and write system calls
  // to consoleread and consolewrite.
  devsw[CONSOLE].read = consoleread;         // dispatch the read to driver consoleread
  devsw[CONSOLE].write = consolewrite;       // dispatch the write to driver consolewrite
}

// Read from file f.
// addr is a user virtual address.
int
fileread(struct file *f, uint64 addr, int n)
{
  // ...
  else if(f->type == FD_DEVICE){
    if(f->major < 0 || f->major >= NDEV || !devsw[f->major].read)
      return -1;
    r = devsw[f->major].read(1, addr, n);
  //...
}

uint64
sys_read(void)
{
  struct file *f;
  int n;
  uint64 p;

  argaddr(1, &p);      // get buffer address argument
  argint(2, &n);       // get number of bytes arg
  if(argfd(0, 0, &f) < 0)       // get fd arg
    return -1;
  return fileread(f, p, n);
}

struct {
  struct spinlock lock;

  // input
#define INPUT_BUF_SIZE 128
  char buf[INPUT_BUF_SIZE];
  uint r;  // Read index
  uint w;  // Write index
  uint e;  // Edit index
} cons;

cons.r – Read Index

    Points to the next character to be read by a process (e.g., the shell or read() syscall).

    Advanced by consoleread() after it consumes a character.

    Sleeps if cons.r == cons.w (i.e., nothing to read).

cons.w – Write Index

    Points to the next position where a new character will be written.

    Advanced by consoleintr() when a character is received (typically from UART via interrupt).

int
consoleread(int user_dst, uint64 dst, int n)
{
  target = n;
  acquire(&cons.lock);
  while(n > 0){

    // cons.r == cons.w means the input buffer is empty (nothing typed yet).
    // It goes to sleep waiting for new input.
    while(cons.r == cons.w){
      if(killed(myproc())){
        release(&cons.lock);
        return -1;
      }
      // sleeps on the address &cons.r and releases the lock while sleeping
      // When an interrupt occurs (user types something), the UART interrupt
      // handler will wake it up via wakeup(&cons.r) (done in consoleintr()).
      // process context will be changed to another process and resumed back
      // once interrupt is hit
      sleep(&cons.r, &cons.lock);

      // now we resumed and will re-check the while loop condition
    }

    // now we have cons.r != cons.w, we read something from uart

    // copy the input byte to the user-space buffer.
    cbuf = c;
    if(either_copyout(user_dst, dst, &cbuf, 1) == -1)
      break;

    // the rest of the code is processing char by char
    // break if we hit EOF, \n, or read n chars.
  }

  release(&cons.lock);

}

void
consoleintr(int c)
{
    switch(c){
    case C('P'):  // Print process list. Ctrl-P
      procdump();
      break;
    default:
      if(c == '\n' || c == C('D') || cons.e-cons.r == INPUT_BUF_SIZE){
        // wake up consoleread() if a whole line (or end-of-file)
        // has arrived. or the input buffer is full
        cons.w = cons.e;
        wakeup(&cons.r);
      }
}

void
uartintr(void)
{
  ReadReg(ISR); // acknowledge the interrupt

  // for input: read and process incoming characters.
  while(1){
    int c = uartgetc();
    if(c == -1)
      break;
    consoleintr(c);
  }

  // for output send buffered characters.
  acquire(&uart_tx_lock);
  uartstart();
  release(&uart_tx_lock);
}

int
consolewrite(int user_src, uint64 src, int n)
{
  int i;

  for(i = 0; i < n; i++){
    char c;
    // copy one byte from user virtual address space to kernel virtual address space
    if(either_copyin(&c, user_src, src+i, 1) == -1)
      break;
    uartputc(c);
  }
  return i;
}

// add a character to the output buffer and tell the
// UART to start sending if it isn't already.
// blocks if the output buffer is full.
// because it may block, it can't be called
// from interrupts; it's only suitable for use
// by write().

void
uartputc(int c)
{
  acquire(&uart_tx_lock);

  if(panicked){
    for(;;)
      ;
  }
  while(uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE){
    // buffer is full.
    // wait for uartstart() to open up space in the buffer.
    sleep(&uart_tx_r, &uart_tx_lock);
  }
  uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
  uart_tx_w += 1;
  uartstart();
  release(&uart_tx_lock);
}

// if the UART is idle, and a character is waiting
// in the transmit buffer, send it.
// caller must hold uart_tx_lock.
// called from both the top- and bottom-half.
void
uartstart()
{
  while(1){
    if(uart_tx_w == uart_tx_r){
      // transmit buffer is empty.
      return;
    }

    if((ReadReg(LSR) & LSR_TX_IDLE) == 0){
      // the UART transmit holding register is full,
      // so we cannot give it another byte.
      // it will interrupt when it's ready for a new byte.
      return;
    }

    int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
    uart_tx_r += 1;

    // maybe uartputc() is waiting for space in the buffer.
    wakeup(&uart_tx_r);

    WriteReg(THR, c);
  }
}

//
// handle an interrupt, exception, or system call from user space.
// called from trampoline.S
//
void
usertrap(void)
{
  // give up the CPU if this is a timer interrupt.
  if(which_dev == 2)
    yield();

}

// interrupts and exceptions from kernel code go here via kernelvec,
// on whatever the current kernel stack is.
void
kerneltrap()
{
  // give up the CPU if this is a timer interrupt.
  if(which_dev == 2 && myproc() != 0)
    yield();
}

// Give up the CPU for one scheduling round.
void
yield(void)
{
  struct proc *p = myproc();
  acquire(&p->lock);
  p->state = RUNNABLE;         // usually from running to runnable
  sched();                     // will switch to scheduler context
  release(&p->lock);
}

// Switch to scheduler.  Must hold only p->lock
// and have changed proc->state. Saves and restores
// intena because intena is a property of this
// kernel thread, not this CPU. It should
// be proc->intena and proc->noff, but that would
// break in the few places where a lock is held but
// there's no process.
void
sched(void)
{
  int intena;
  struct proc *p = myproc();

  if(!holding(&p->lock))
    panic("sched p->lock");
  if(mycpu()->noff != 1)
    panic("sched locks");
  if(p->state == RUNNING)
    panic("sched RUNNING");
  if(intr_get())
    panic("sched interruptible");

  intena = mycpu()->intena;
  swtch(&p->context, &mycpu()->context); // switch from process context to cpu sheduler context
  mycpu()->intena = intena;
}

// Saved registers for kernel context switches.
struct context {
  uint64 ra;
  uint64 sp;

  // callee-saved
  uint64 s0;
  uint64 s1;
  uint64 s2;
  uint64 s3;
  uint64 s4;
  uint64 s5;
  uint64 s6;
  uint64 s7;
  uint64 s8;
  uint64 s9;
  uint64 s10;
  uint64 s11;
};